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| L6363 PRML READ/WRITE CHANNEL PRODUCT PREVIEW s SIGNAL PROCESSING - PR4 signal equalization and loops - 8th order optimized low pass filter with programmable cut-off frequency and boost - single flash 6-bit ADC - 5-TAP programmable/self-adaptive digital FIR for signal equalization - Programmable/self-adaptive Offset and MR Head Asymmetry compensation for signal equalization - Timing and Gain loops for optimum data recovery - Encoder scheme: - Rate 304/338 with Local ECC (16/17 without Local ECC) - Detector scheme: - Media Noise TerminatorTM Detector - Optional Local ECC Post Processing scheme - 8-bit NRZ interface to disk controller - Thermal Asperity detection/compensation and Erasure Flag s TQFP100 ORDERING NUMBER: L6363 CHANNEL QUALITY MONITOR - Fast read parameters optimization for minimum BER - Advanced Disk Surface Defect Scan QUALITY AND RELIABILITY - BIST for analog front-end and digital back-end - Iddq and I/O pins mapping POWER SUPPLY AND CONTROL - 2.5V Analog and 1.8V Digital supply; 1.8V to 3.3V supply for I/O pins - Advanced Power Management features s s s WRITE - 2 level Write Precomp for Non Linear Transition Shift compensation - Asynchronous and Synchronous Direct Write for disk/head characterization DESCRIPTION L6363 is a 0.18m CMOS PRML R/W channel supporting data rates up to 750Mb/sec with Servo Demodulation, Clock Synthesis, Channel Quality Monitor for channel optimization and Disk Surface Defect Scan capability s SERVO - Digital Synchronous Servo with data rates up to 75MHz (8x Ovsersampling) - Internal Burst and Grey Code detection - Repeatable Run Out Support June 2001 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/4 MUX 2/4 LPFCA WOP WOM BDAC Write Precomp SMD FCA FDAC MRA HPF Low Pass Filter OFF ADC FIR SRC Data Detector ECC Timing Loop Servo Detector Offset Loop Asymm. Loop Gain Loop WCLK NRZ[7:0] Encoder Decoder Interface SBD* ER_FLAG TA_OUT ODAC Thermal Asp. Detection & Control Zero Phase & Gain Restart Clock Generator Servo Burst Demod. Servo Interface SVOCLK SVO[1:0] SCLK Data Freq. Synthesizer Control Block Digital Test Block Interface SDEN SDATA SG RG WG PWD TI-[5:0] RRCLK RESET* TBUSCLK MODE[1:0] TESTBUS[7:0] L6363 DIAG1 Analog Test Point Figure 1. Block Diagram DIAG0 INP Zin INM Ctrl VGA GDAC MDAC IREF Bandgap EXTCLK Servo Freq. Synthesizer REFCLK L6363 DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.17 0.09 mm TYP. MAX. 1.60 0.15 1.40 0.22 1.45 0.27 0.20 16.00 14.00 12.00 0.50 16.00 14.00 12.00 0.60 1.00 0.75 0.018 0.002 0.053 0.007 0.003 MIN. inch TYP. MAX. 0.063 0.006 0.055 0.009 0.057 0.011 0.008 0.630 0.551 0.472 0.019 0.630 0.551 0.472 0.024 0.0393 3.5(min.), 7(max.) 0.030 OUTLINE AND MECHANICAL DATA TQFP100 D D1 D3 A A2 A1 75 76 51 50 0.076mm .003 inch Seating Plane e E3 E1 E B PIN 1 IDENTIFICATION 100 1 25 26 K TQFP100M C L L1 3/4 L6363 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 4/4 |
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